Paper
K. Flanagan, J. Archibald, and J. Su. Low power memory hierarchies: An
argument for second-level caches. Microprocessors and
Microsystems, 21(5):279-290, February 1998.
Abstract
With the availability of high-performance, low-power microprocessors,
portable computing is becoming commonplace. The prevalence of portable
computers makes them the most obvious examples of systems in which power
requirements are a significant design issue. This paper addresses the
power tradeoffs of an important component of modern memory hierarchies:
second-level caches. Thought by some to increase the total system
power requirements, second-level caches can actually reduce the
power consumed by the memory hierarchy--in addition to improving the
overall performance. Power is saved by substituting second-level cache
accesses for main memory accesses; given current memory technology, an
active second-level cache and an idel main memory require less total power
than an active memory by itself. Clearly the amount of power saved
depends on the extent to which main memory accesses are reduced.