Paper
G. Thompson, B. Nelson, and K. Flanagan. Transaction processing
workloads- a comparison to the SPEC benchmarks using memory hierarchy
performance studies. In IEEE International Workshop on Modeling,
Analysis and Simulation of Computer and Telecommunication Systems,
pages 152-156. IEEE, 1996.
Abstract
This study analyzes the memory hierarchy performance of three SPEC
benchmarks and two TPC benchmarks. It finds large differences between the
benchmarks in instruction cache miss rates and smaller differences in data
cache miss rates. It then breaks all of the miss rates down in their
components: context switch misses, user misses, supervisor misses, and
collision misses. It demonstrates that context switches contribute little
to the miss rates as do collision misses. Finally, using temporal
locality graphs, it shows that the inherent locality differences between
the reference streams is the main cause of miss rate differences between
the various benchmarks.