PEL Homepage
Research Projects
DiskIO Performance

Instruction Trace Generation
Internet Performance
Locality Surfaces
Low Power Systems
PEL Object Devices


Performance Evaluation Laboratory


RETHINKING THE STORAGE HIERARCHY

We believe that the advent of mainstream processors with large (>1TB) physical address spaces presents an opportunity to re-evaluate the storage hierarchy in personal computers. We are in the process of building a PCI-Express card which can be mapped into memory space for exploring disk and memory usage patterns. We want to explore the inclusion of different memory types into the main memory hierarchy.

CURRENT DESIGN

We are planning to use a HiTech Global Virtex 4 Board as soon as they are available. The current expected shipping date is April 2006. This board is a flexible platform with DDR2, SATA, USB 2.0, PCIe, SD card, Gigabit Ethernet, RocketIO, and General Purpose I/Os.
  • We are searching for an affordable PCIe core
  • We plan to use the MiG (Memory Interface Generator) from Xilinx
  • We are looking for the best way to interface to a hard drive
    • SATA (expensive IP core)
    • Gb Ethernet
    • USB 2.0 (can Cypress controller be a host?)
    • Others?

OTHER POSSIBILITIES

  • HyperTransport design in Opteron Socket (expensive IP core)
  • IO/Network processor design (inflexible mappings)
    • Intel IOP 80332
    • Freescale MPC8548E
    • Intel Xscale

© 2006, Performance Evaluation Laboratory, Brigham Young University. All rights reserved. Reproduction of all or part of this work is permitted for educational or research use provided that this copyright notice is included in any copy. Send comments to webmaster@pel.cs.byu.edu.