Altera HyperTransport MegaCore

From PEL Wiki

This is mainly a quick reference for using the HT Megacore while working on My FPGA design page

xd1000_ht_core.vho is only for simulation. There's no need to make it before compilation of the FPGA design.

BarHit_o[2:0] is an encoding of which Base Address Register was hit
- For my device, I'm interested in these encodings:
  - '000' 64-bit BAR01 (XD1000 interface)
  - '010' 32-bit BAR2 (8kB dual SATA interface)
  - '011' 32-bit BAR3 (32-bit dual IDE interface)
  - '100' 64-bit BAR45 (256GB interface)

I'd like to changed the values of the Vendor ID, Device ID, Class Code, etc. so that it appears to be a memory device instead of just an unclassified non-vga device.

These values are set in the encrypted verliog files, however, so I guess I won't.

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Interface

The Altera HyperTransport Megacore takes the Receive and Transmit interfaces from HT and splits them into 6 "Atlantic" interfaces. Atlantic is an Altera standard, which was designed for packet interfaces. The commands and data go on the same bus, and SoP (start of packet) and EoP (end of packet) delimit the packet boundaries. For my device, I need to be able to use RxP RxNP TxR for the CPU communicating with me, and TxP TxNP and RxR for communicating with the disk, or interrupting the CPU.