DIMMs on DiskRAM

From PEL Wiki

The difficult part here is trying to understand which decisions were made by the XD1000 team for performance reasons, and which were made for simplification.

The way the demo is set up, there are two DMA engines for HyperTransport and two for the DIMMS. Since this is the most important part of my design, I need to combine them.

I need to figure out the best way to do that. One interesting part is the control bus that isn't directly connected to anything. It goes through the HT_CTRL_IF which decodes control cycles and assigns them to components. I think I need to avoid this interface, and directly respond to the read and write transactions.

I'm trying not to break their example while I mess around because I want to be able to flash the FPGA from the Host, and the easiest way is to leave that code intact.