Data Hazards in DiskRAM
From PEL Wiki
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Types of Transactions:
R = Read A = After W = Write
- RAR = no hazard
- WAW = writes always complete in order with respect to other writes
- RAW = hazard, but since I'm buffering writes, reads to the same location should be caught at the highest level.
- I need to take some care here to make sure that evictions from the buffer don't pass a later read.
- WAR = hazard, since I buffer writes, writes don't get propagated, so as long as the write waits until the read checks the buffer, it should be OK.
- Again, if there is an eviction from the write buffer, that could cause problems with an earlier read.
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Solutions
- Let each level handle coherency (pass ordering information or order bus)
- Have a master which doesn't allow units to see transactions out of order if they are RAW or WAR
Categories: Myles | Pel | FPGA
