DiskRAM

From PEL Wiki

My project right now is DiskRAM. Arguments for DiskRAM lists some of the ways to approach the rationale for DiskRAM. In short, the idea is that disk has been artificially separated from memory. There is no inherent difference between the data that is stored in memory and on the disk (think swap, file caches, etc.) If we unify disk and memory (DiskRAM) we can globally optimize their interactions. Interesting Papers is a page where we try to keep track of papers that support our research.

Here are the Sticky Notes I was keeping and a News Page that I hope will help me keep track of related news in industry. I've also decided to keep copies of Myles Works In Progress to make it easier to get feedback. My NSF Page is another useful one. Things I Am Doing tries to keep me organized.

Study Ideas is a page about different studies and ways to approach them.

Implementation Options is the page where I'm currently collecting and shooting down ideas. One of the main questions we have is: "What does implementing it in hardware prove that simulation doesn't?" I feel that people trust simulations less than they trust hardware results for performance. Since it's a trust issue, there's no hard evidence.

If we want to make the case that persistence is all we care about, and performance is secondary that might be an easier sell with the simulator.

Once we make this work, will the scheduler have to be significantly changed? Does the fact that there are fewer/no page faults break the algorithm? Should timer ticks come more frequently?

Since we've chosen FPGA Implementation, here is the My FPGA design page.

For the board, we need to keep track of Pin Counts And Other Messy Details.

One way to implement it is to buy a "super computer" from Cray or SRC Computers. There are some reconfigurable computers that allow the FPGA to be mapped into the memory space. Unfortunately, that isn't what they were meant for, so they don't come ready for that kind of reconfiguration off the shelf, but at least all the hardware is there. It turns out that it would only be a small change to their reconfigurable logic, but Cray's target market for these computers is $2-3M, so they're not interested in letting me have one with the change implemented
Another implementation option comes from HP or Intel. They both have hot-plug memory cards that could be used for an implementation of DiskRAM. HP's implementation is a little older, and has a wide, slower bus to connect it to the chipset. Intel's is a narrow, fast bus. Both are proprietary, but HP's is at the end of its life, so they may be more willing to share.
Now there are two other companies DRC Computer and XDI (theXD1000)with the Cray type hardware that plugs into an Opteron socket.

My Experiments is a page that documents each experiment that we undertake.

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DiskRAM in the FPGA

Once I have the hardware, there are several stages of implementation.

1. Direct-mapped

The first stage is to implement DiskRAM as a direct-mapped cache. In this scenario, the disk is addressed directly and the memory caches it in a simple scheme. The pros are that it is a simple design and will let me work out some kinks, the con is that there is no indirection. The indirection enables fast freeing, relocations, and replications.

2. TLB-based

I need to figure out how to make the directory fast and small. One way is to use page tables and a TLB. As long as my TLB is larger than the processors', I can still get some performance benefits. There are some interesting questions, such as

3. Emulate Software

I could just implement the current paging algorithm in the FPGA using more information than is available to the OS.

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DiskRAM (the larger vision) and my piece

In unifying storage, I believe that there are benefits from crossing the line from RAM to disk and disk to RAM. In other words:

The ideal device is a hard drive with a RAM interface and a large DRAM cache

Realistically, in my PhD work, I won't integrate them that closely. Interfacing with a raw disk so that I can optimize placement and replication is another PhD topic. That said, it would be nice if I could somehow estimate the upper bound of performance.

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