DiskRAM Optimizations
From PEL Wiki
- Use the other interface to SRAM to implement a cache-is-RAM idea. I can manipulate the tags and status to make it appear that the DRAM has valid data from disk in it, zero it, and then it can be written back.
- Make DiskRAM something other than direct-mapped.
- This is important because it thrashes badly!
- Implement Copy-on-write
- Zero page optimizations
Categories: Pel | Myles | FPGA
