FPGA Hints
From PEL Wiki
- Make sure all state machine inputs are in the same clock domain. Otherwise routing differences can cause the state machine to enter two states at once (This is bad)
- Try not to use "showahead" modes in FIFOs. It's not worth the extra delay
- Partitioning the design reduces compilation times by quite a bit.
Categories: Myles | FPGA | Pel
