FPGA Implementation

From PEL Wiki

Image:OpteronFIGS.pdf

This is the block diagram of the motherboard

This is the block diagram of our DiskRAM prototype, which occupies the same space as one Opteron in the motherboard diagram

There are two companies which came out with their implementations of this in April 2006. DRC Computer and XtremeData, Inc. I'm pretty excited, hoping that one of them will decide to sell me one.

In this scenario, the only cores needed are a HyperTransport tunnel, DDR400 interface, and QDR SRAM interface (free from xilinx). If we can use a PCIe SATA card instead of adding a SATA controller on board, it should make our solution more flexible and simpler.

Xilinx and Altera have DDR400 (PC3200) and QDR II 300 MHz controller cores for their chips.

Altera has a HyperTransport core, but it is 8-bit. Xilinx farmed theirs out to GDA

I need to find out prices and chip utilization for each of the cores. Hopefully I can find a chip that integrates all three at a reasonable price.

Nuvation has IPCores for ATA-5 and SATA for Altera and Xilinx FPGAs